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The purpose of this paper is to design an on-chip inductor with high inductance, high-quality factor and high self-resonance frequency for the equivalent on-chip area using fractal curves.

A novel hybrid series stacked differential fractal inductor using Hilbert and Sierpinski fractal curves is proposed with two different layers connected in series using vias. The inductor is implemented in Sonnet EM simulator using 180 nm CMOS standard process technology.

The proposed inductor reduces the parasitic capacitance and negative mutual inductance between the adjacent layers with significant improvement in overall inductance, quality factor and self-resonance frequency when compared with conventional series stacked fractal inductors.

The fractal inductor is used to create high inductance in the single-layer process, but access to multilayers is restricted owing to unusual and expensive fabrication processes.

The proposed inductor can be used in implementation of low noise amplifier, voltage controlled oscillators and power amplifiers.

This paper introduces a combination of two fractal curves to implement a hybrid fractal inductor that enhances the performance of the inductor.

The purpose of this study is to develop a high-quality factor fractal inductor for wireless applications such as satellite, WLAN, Bluetooth, microwave, radar and cellular phone.

The Hilbert fractal curve is used in the implementation of the proposed inductor. In the proposed inductor, the metal width has split into multiple paths based on the skin depth of the metal. The simulations of the proposed inductor are performed in 180 nm CMOS technology using the Advanced Design System EM simulator.

The multipath technique reduces the skin effects and proximity effects, which, in turn, decreases the series resistance of the inductor and attains high-quality factor over conventional fractal inductor for the equal on-chip area.

The width of the path has chosen higher than the skin depth of the metal for a required operating frequency. Due to cost constraints, the manufacturing of the proposed fractal inductor is limited to a single layer.

The proposed inductor will be useful for the implementation of critical building blocks of radio frequency integrated circuits and monolithic microwave integrated circuits such as low-noise amplifiers, voltage-controlled oscillators, mixers, filters and power amplifiers.

This paper presents for the first time the use of a multipath technique for the fractal inductors to enhance the quality factor.

This paper aims to present an efficient method to improve quality factor of printed fractal inductors based on electromagnetic band-gap (EBG) surface.

Hilbert fractal inductor is designed and simulated using high-frequency structural simulator. To improve the quality factor, an EBG surface underneath the inductor is incorporated without any degradation in inductance value.

The proposed inductor and Q factor are measured based on well-known three-dimensional simulator, and the results are compared experimentally.

The proposed method was able to significantly decrease the noise with increase in the speed of radio frequency and sensor-integrated circuit design.

Fractal inductor is designed and simulated with and without EBG surfaces. The measurement of printed circuit board prototypes demonstrates that the inclusion of split-ring array as EBG surface increases the quality factor by 90 per cent over standard fractal inductor of the same dimensions with a small degradation in inductance value and is capable of operating up to 2.4 GHz frequency range.

This paper aims to model the coupled on-chip Copper (Cu) interconnects by using the multiresolution time-domain (MRTD) method.

The proposed model is a wavelet-based numerical method for analyzing signal integrity and propagation delay of coupled on-chip interconnects. Moreover, the dependency of crosstalk noise and delay on coupling parasitics (L12, C12) are analyzed.

The proposed MRTD method captures the behaviour of propagation delay and peak crosstalk noise on victim line against coupling parasitics, which is in close agreement with that of H simulation program with integrated circuit emphasis (HSPICE). The average error for the proposed model is less than 1 per cent with respect to HSPICE for the estimation of peak crosstalk noise voltage.

Simulations are performed using HSPICE and compared with those performed using the proposed MRTD method for global interconnect length with 130-nm technology, where the computations of the proposed model are carried out using Matlab.

The MRTD method with its unique features is tailored for modelling interconnects. To build further credence to this and its profound existence in the latest state-of-art works, simulations of crosstalk noise and propagation delay, for coupled Cu interconnect lines, using MRTD and finite-difference time-domain (FDTD) are executed. The results illustrated the dominance of MRTD method over FDTD in terms of accuracy.